Because of critical timing requirements in electronic circuits such as communication systems, clock recovery circuits, frequency multipliers, and data synchronization circuits, locally generated clock signals must be accurately synchronized with a reference waveform. A Phase-Locked Loop (PLL) is a feedback control system that adjusts the phase or frequency of a locally generated signal to match the phase and frequency of an input “reference” signal within a period called “lock time.” In general, a PLL is used to take a low-frequency off-chip clock and generate a high frequency on-chip clock. A Delay Locked Loop (DLL) is similar to a PLL in that a DLL is designed to generate an output signal at a prescribed delay with respect to an input reference signal.
Typically, a PLL has three components: a phase/frequency detector (PFD), a loop filter (LF), and a controlled oscillator (CO). The CO could be voltage-controlled (VCO) or current-controlled (ICO). The output of the CO is fed back to the PFD. The frequency of the output signal is usually a multiple of the input reference frequency. In addition to the three components stated above, a PLL may also include a charge pump (CP), which manipulates the amount of charge on the filter's capacitors depending on the signals of the PFD. In other words, the PFD produces a signal, which increases or decreases charge output by the CP, which adds or removes charge from the LF capacitor. The CO produces an output clock with a frequency proportional to the voltage or current input to the CO.
PFD/CP converts phase (or frequency) error into current and enables locking output frequency to input frequency. The LF operates on the PFD/CP output current to generate a voltage, which controls the frequency output at the CO. The CO output is fed through programmable dividers then back to the PFD. Because of its feedback nature, the PLL drives the CO until the error at the PFD is zero.
A loop filter may include a resistor and two capacitors—a damping capacitor and a parasitic bypass capacitor. As magnitude of the damping capacitor increases, the area of the integrated circuit increases. It is desirable to increase the effective damping capacitor magnitude without increasing the area. Because the capacitors take up the bulk of the area in a PLL, one may reduce the area of a charge-pump PLL by reducing the area of the damping capacitor C1, and the area of the capacitor associated with auto-calibration loop. One way to reduce the capacitor size is to reduce the gate oxide of the device used to make the integrated capacitors, which allows for a much smaller area for a desired capacitance. But thinner gate oxides lead to gate leakage currents, which in turn cause static phase offset. A technique to alleviate static phase offset is described in U.S. Pat. No. 6,043,715, but this method increases the area, thereby negating the goal of reducing the area. A second method is to use a smaller capacitance value, thereby obtaining a smaller area, but this may cause changes in loop dynamics of the PLL, affecting its closed-loop performance adversely. A third method uses two charge pumps, one for proportional component and one for integral component of loop filter voltage. But the area of the second charge pump and the circuitry required to sum the two separate capacitor voltages counteracts any savings obtained by reducing the size of the capacitor. As we have seen, none of the known methods achieves the goal of reducing the area of a charge pump PLL without undesirable results. Accordingly, there is a need for an improvement in the art.